-
Got my new Pocket Analog and installed this but am unable to get it to work. Just seems to produce random static. Just using a basic adventure cart. I am also unable to locate the vavoxrom.bin avoxee.…
-
Hi!
So here is a single core BP Verilog file generated by [bsg_sv2v](https://github.com/bespoke-silicon-group/bsg_sv2v). I'm trying to run it through the flow, but I'm getting strange Yosys errors. A…
-
I've found a minor but reproducible graphical glitch in the Densha de Go! route selection menu.
#### Expected Behaviour
The route selection menu should show four square train icons.
#### Curr…
-
> To generate the .rom format binaries used by this core, you must use the MRA files included in this repo, along with the corresponding ROMs from the most recent MAME release.
Took almost an hour …
-
Hi @tangxifan , I have an issue with a fairly basic benchmark for you
I have a benchmark
```
module test (
input clk,
input reset_n,
input a,
input b,
output c,
output reg c_…
-
### GitHub Username
spiritualized1997
### Repository Name
openFPGA-GB-GBC
### Pre-release
- [ ] The GitHib release which contains the openFPGA core is labeled as a pre-release.
### Asset Filter
…
-
Booting the game results in "Error" message.
I also get the same behavior on an ED-GB flashcart
-
@tangxifan @ganeshgore ,
VPR has an optional argument: --flat_routing true
Is OpenFPGA ready to support this option?
If yes, are there any specific properties the vpr.xml, openfpga.xml arch file…
-
### Core Author username
nullobject
### Core .yml snippet
```yml
display_name: Tecmo
repository: openfpga-tecmo
```
-
> **Describe the bug**
When I create an FPGA layout with I/O in the center instead of around the edge, and set the corners to CLB, an assertion fails in openfpga/src/fabric/module_manager.cpp. Below …