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The design is generated from a [simple LiteX demo](https://github.com/enjoy-digital/liteiclink/blob/master/bench/serdes/versa_ecp5.py) generated using the latest-ish commits. I have attached the gener…
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incident: https://app.incident.io/incidents/260
affected cluster: `us72`
We noticed that new workspace got stuck in INITIALIZING (their content readiness probe failed), piods had status RUNNING.
The …
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Summary: Nextpnr throws Assertion failure: str.back() == '"' (/work/_builds/linux-x64/nextpnr-ecp5/nextpnr/ecp5/lpf.cc:49)
Steps to reproduce:
1) Clone my repository from github:
$ git clone git@…
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## Environment
- Development Kit: [none]
- Module or chip used: [ESP32-WROOM-32D]
- IDF version (run ``git describe --tags`` to find it): v4.4.1-405-g6c5fb29c2c
- Build System: [idf.py]
…
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Hello,
i tried to test the Lib with Platformio and compile the Examble "direct_io_pin.ino"
My version of PlatformIO ist 3.1.0 Core 4.2.1
I use an Arduino DUE an Programming Port tis ist Atmel SAM …
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I am trying to place and route a simple nand module for `LFE5U-25F-6BG256C`:
top.v:
```
module top(
input a,b,
output c
);
nand(c,a,b);
endmodule
```
top.lpf:
```
LOCATE COMP "a"…
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I am beginner to Zephyr rtos.
I have one SAM V71 Xplained Ultra board and testing sample program on it.
Also, I have a new board using SAMV71N21 chip we made.
I modified sam_v71_quant-common.dtsi t…
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In the current APIO/develop branch the arachne-pnr has been replace by **nextpnr**
The FPGAs resources were obtained by parsing the arachne-pnr output
As an example, this is an output for the ic…
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After changing the IP addr at liteeth.yml and
make ../liteeth_core.v
when I make top.svf again, i get the error below
Info: Packing IOs..
Info: pin 'CLK$tr_io' constrained to Bel 'X72/Y2/PIO…
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I cant't seem to compile with V8.0 pinout. I have changed the top.lpf to match version 8.0 pins.
Info: Packing IOs..
Info: pin 'CLK$tr_io' constrained to Bel 'X0/Y32/PIOD'.
Info: pin 'B$tr_io' co…