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Copied from https://github.com/joxie/riscv-debug-security/issues/18
@gokhankaplayan
Performance counters has configuration registers (mcyclecfg, minstretcfg) to isolate between privilege levels…
joxie updated
6 months ago
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Performance counters has configuration registers (mcyclecfg, minstretcfg) to isolate between privilege levels. HW RoT should be able control global enable for performance counters. For example, medbge…
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If Smmtt also supports M-mode only or M/U mode systems, where S-mode is absent, adding some description or diagrams for those use cases is helpful to people.
_Originally posted by @gagachang in htt…
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It would be helpful to have a glossary for the abbreviations used in this specification (e.g. TCB).
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Reference: [link](https://lists.riscv.org/g/tech-ap-tee/message/128)
> For Supervisor Domain memory isolation, the Smmtt extension may be used for deployment scenarios **where the TSM is at the sam…
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Reference: [link](https://lists.riscv.org/g/tech-ap-tee/message/128)
Ref Figure 4
This logic does not include the (optional) finer-grained access control restriction in SmMTT PTEs (in particular…
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Hi guys,
We are working a complete OpTEE solution for RISC-V, and now are able to boot opensbi + optee + uboot + linux, and able to pass all the optee test suites and benchmark(except network relat…
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Just as discussed in external debug TG meeting on Jan 30th, it is agreed to move the ISA part to smmtt spec. File the issue to track progress.
I think we need a chapter in smmtt to fit in and rephr…
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According to Priv. Spec.: *Machine Trap Delegation Registers (medeleg and mideleg)*:
```
mideleg holds trap delegation bits for individual interrupts, with the layout of bits matching those
in the …
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Reference: [link](https://lists.riscv.org/g/tech-ap-tee/message/128)
> There are two deployment models possible here. CoVE ABI is equally applicable for
both modes - this specification focusses on…