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**Description**
There are now new attributes for declaring SPIR-V builtins, etc.
But no documentation how to use them yet.
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```
target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v16:16:16-v24:32:32-v32:32:32-v48:64:64-v64:64:64-v96:128:128-v12
8:128:128-v192:256:256-v256:25…
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By design, it's possible to generate arbitrary and therefore invalid SPIR-V with inline SPIR-V. In this case, validation errors are much less likely to be the result of compiler bugs, so we should rem…
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**Description**
Two inputs or outputs can have the same location as long as they have different components. DXC is currently unaware of the component and will issue an error if two inputs have the …
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Thread init guards are generated for local static variables when using the Itanium CXX ABI. This ABI is also used for SPIRV generation, but at least for HLSL targets doesn't need the corresponding `__…
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**Description**
When unrolling a loop, if I pass a value to it to specify the max number of iterations the loop should execute (as specified [here](https://learn.microsoft.com/en-us/windows/win32/dir…
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Following my AR from OpenCL Tooling TSG. The translator claims SPIR-V 1.4 support, yet there are few features missing
- [x] `OpCopyLogical` instruction
- [x] `OpPtrEqual `and `OpPtrNotEqual` instr…
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```
target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v16:16:16-v24:32:32-v32:32:32-v48:64:64-v64:64:64-v96:128:128-v12
8:128:128-v192:256:256-v256:25…
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### What happened?
When compiling CLIP Text Encoder 1 ([stable_diffusion_xl_base_1_0_64_fp16_clip_1.mlir](https://storage.googleapis.com/shark-public/ean/sdxl-turbine/stable_diffusion_xl_base_1_0_64_…
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While running the QuickSilver app with Levelzero as backed I see a crash. Looks like "__atomic_fetch_add_8" support is missing.
QuickSilver : https://github.com/oneapi-src/Velocity-Bench/tree/main/…