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Converting some tests to ChiselSim, I've noticed the tests run about 20x slower than chiseltest.
As a comparison, running on ChiselSim:
```
❯ time ./mill chiselv.test.testOnly chiselv.ALUSpec
…
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#### Description
When the interface counters exceed 10^14, the portstat utility gives traceback. So the "show interface counter" gives the traceback.
```root@yy39top-lc4:/home/cisco# sonic-clear c…
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It would be helpful if `cocotb.triggers.Timer` could precisely match unit-less verilog delays, which are multiples of the simulator time unit. For instance to write assertions on the value of `q`:
…
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**Description:**
The current Python script for BOOLCFG(UI-PYTHON) validates the functionality of the test cases. but, the descriptions of the test steps are not user-friendly and may be difficult to …
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### Description
There are some gaps in the config files for the `cw310` interface which goes through the SAM3X.
* Some pin names are not recognised, leading to errors like `Error: Invalid pin na…
jwnrt updated
4 months ago
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Could you provide the saliency map on the SOD test datasets?such as ECSSD/DUT-TE/DUT-OMRON/PASCAL/HKU-IS? Thank you for your contribute to SOD field.
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| | |
|--------------------|----|
| Bugzilla Link | [PR50238](https://bugs.llvm.org/show_bug.cgi?id=50238) |
| Status | NEW |
| Importance | P normal |
|…
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### Technical Group
Privileged Spec IC
### ratification-pkg
Priv 1.13
### Technical Liaison
Greg Favor
### Task Category
Arch Tests
### Task Sub Category
- [ ] gcc
- [ ] bi…
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The code in the `binary` module needs a refresh - it's currently a bottleneck in small intensive simulations and doesn't provide all of the features it should. As per issue #119, we need to minimise …
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### Description
If one awaits a trigger with dut as the signal (e.g: `await RisingEdge(dut)`), then the error produced is incomprehensible:
```
./sample:error: NULL access dereferenced
in process …