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I try a lot of version for iscv-gnu-toolchain, only Some Version can build this project
https://github.com/riscv-collab/riscv-gnu-toolchain/tree/2023.01.03
Code in boot.s can not be compile, I don…
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I have encountered illegal instruction exception due to overlapping registers in vector crypto test i.e vsha2ms-e32.vv-01 (line 73). Replacing that with other register resolved the issue
```
inst_8:…
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Hi,
CHERIoT is spec'ed as being 16 GP registers only. However, in Sonata the RV32E is set to 0 which means that there are 32 GP registers. Shouldn't the RV32E parameter be set when the CHERIoTEn pa…
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Is there a plan to split the `fnmadd.d_b15`, `fmadd.d_b15`, `fmsub.d_b15`, and `fnmsub.d_b15` in `rv32i_m` test case to what was done in commit `0d6fa5ca1dceaa916180d7d800781ca67a554931`?
While per…
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Negative immediates aren't getting covered properly.
The rv32i covergroup contains a cp_imm12 coverpoint with 12-bit 2's complement immediates. The values >=2048 thus are effectively negative. The…
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I'm currently looking through the [RISCV reference files](https://github.com/Minres/RISCV_ISA_CoreDSL/blob/master/RV32I.core_desc#L12) and I'm already spotting potential for improvement. The very firs…
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I use Z-System (NZCOM) with z80pack on my Linux machine and have come to rely on the z80pack RTC for timestamping support. Unfortunately, the pano_z80 BIOS doesn't seem to have implemented it and I g…
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### Posting because I cannot find mention anywhere
I have seen that mono supports the RISC-V architecture but cannot find anything relating to .NET 5 support for RISC-V.
Are there any plans to sup…
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I can't figure out what mechanism is used to select what test suite is actually compiled.
Or, what toolchain is used. For instance I am using the `buildroot` toolchain.
Additionally, I don't se…
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my co-worker told me that wasmtime project wanted to hear use-cases/demands/requirements for embedded scenarios.
here is FYI about our requirements.
#### Feature
support embedded environment
…
yamt updated
6 months ago