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Please post the next blog on the OpenHW Blog page - Date March 30
Ensuring Correctness and Quality of RISC-V Testbenches
Gabriel Raducan, R&D Team Lead, AMIQ EDA
When most people think about O…
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1. Never use timescale/timeunit statements in rtl code. Even in testbenches its better to just pass an argument setting timescale/timeunit in the simulator.
https://github.com/andreaskuster/axi-io-pm…
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This is a reach I think (given the maturity of the project) but do you guys have IPs (or whatever you might call them in this context) for communicating between modules? E.g., something along the line…
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SiliconCompiler is an open-source Python-based build system for ASIC design tools.
## Several pipecleaner designs
For this project, we would like to build a variety of small but realistic digita…
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Example: https://mila.quebec/en/publications/
It would be nice to reuse the same code as in the Mila website. Not sure if that's 'easily' possible via RTD
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cocotb == 1.5.0
operating system == Linux x64
simulator == QuestaSim 64 10.7f
Python == python3
RTL language == SystemVerilog
Hello,
Top-level of project contains AXI Interface (by Interface…
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This issue is for the discussion and coordination of a proposed redesign of the implementation of scheduling of internally derived events (often referred to as generated clocks) in Verilator.
# Bac…
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This is an idea for a schema (algorithm) to convert arbitrary procedural
code written in the body of a SystemVerilog process (as defined in IEEE
1800-2017 Chapter 9), containing blocking constructs …
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Currently, we can roundtrip Calyx programs between the [native][] infrastructure and the CIRCT dialect for Calyx. This means that we can, in essence, run Calyx optimizations in both the systems and th…
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Hello,
I'm a little bit confused about the purpose of `ExpandWhens` pass in Firrtl, which runs before the IR is lowered to HW. It seems to me that it tries to convert a more high-level construct (i…
Kuree updated
2 years ago