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Filing this Issue with two Compiler Explorer testcases - one in LLVM IR and the other in C.
# LLVM IR testcase
Compiler Explorer link: https://godbolt.org/z/3Wf1cfEo1
Problem: when the parent…
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The way swizzles are implemented on vectors and matrices is UB due to the strict aliasing rule. This is how the vector data is defined:
```
union
{
n128 vec;
float f32[1];
#inclu…
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Currently, several of the OCIO ops have a code path that uses Intel SSE intrinsics (SIMD instructions) for faster performance. However, on Mac M1/ARM chips, these don't work and so the slower straigh…
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Use xy-vsfilter's SSE2 implementation and Intel's AVX implementation when applicable. Write a NEON implementation for ARM, and possibly an SSE4-or-such implementation (but probably not :|). Probably c…
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This is rather important. Many platforms don't have SIMD at all. Original pre-Intel Hyperscan did include a C backend, we plan to reenable that. This would also be a good indication of how much faster…
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Hello Ryan,
first of all - a BIG THX for this lib. After some video lectures i started with SIMD-stuff and found nimsimd a perfect start. AVX512 is missing, but state-of-the-art AVX2 surely has the…
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arch specifics.
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redis : redis-stack-version:lates ,it run on docker
below is the crash report
```
-- | --
Thu, May 18 2023 9:12:58 pm | 9:C 18 May 2023 13:12:58.787 # oO0OoO0OoO0Oo Redis is starting oO0…
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The Rustonomicon defines a data race like so:
> - two or more threads concurrently accessing a location of memory
> - one of them is a write
> - one of them is unsynchronized
AIUI, all data race…
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On http://www.rawtherapee.com/downloads/, currently, for mac OS, there is only 64bit install package.
So please provide install package for Mac M1 (new ARM-based architecture) CPU. Thanks.
…