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The reference says:
``` text
class ConcatSignal(*args)
This class creates a new signal that shadows the concatenation of its parent signal values.
You can pass an arbitrary number of signals to the …
josyb updated
9 years ago
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MyHDL code below:
```
#!/usr/bin/env python
from myhdl import *
W = 4
def myhdl_b3(in1, s, out1):
t = (2,5,9,14)
@always_comb
def rtl():
out1.next = in1 + t[s]
return rtl
in1, out1 …
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Applies to MyHDL 0.9.
If a constant value is given as an argument that is then assigned to a signal in an enclosed process, conversion to VHDL will generate a VHDL constant for that variable. If this …
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Presumably the problem is that pip isn't grabbing the correct code.
Quite possibly this is something I'm doing wrong on my end but I thought I'd post just in case, since probably most people aren't us…
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MyHDL does not seem to like running with Python 3 earlier than 3.4:
```
# New pipes are not inheritable by default since py 3.4
if not PY2:
for p in rt, wt, rf, wf:
> …
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Fail to generate verilog code for the below code
``` haskell
topEntity :: Index 49 -> Index 49
topEntity x = x `div` 2
```
Besides, I write `topEntity x = x`div`2` because `Index` is not Instance of…
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I'm new at myhdl so most probably I'm doing something wrong but from the rs232_tx example I think what I'm trying should be possible.
I have defined a constant with an integer value. Then, I use thi…
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I have a [project](https://github.com/cfelton/minnesota) that fails with the latest code on the master branch. According to git bisect the bug was introduced in 08519b4 [rename attribute ref in the A…
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https://gitter.im is a nice chatroom integrated with github. I think it will provide a nice addition to the issue tracker and promote discussion. example: https://gitter.im/neovim/neovim
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When `TristateSignal`s are used as top-level ports the signal is not converted to an `inout` when the target is Verilog. This appears to work in VHDL but not in Verilog.
In addition PR #74 appeared…