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hi ,
I cant find any web site to order these....
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- New icetime does not need chipdb PREFIX. Instead `icetime -C `
- Yosys 0.7 release
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There are various different methods of 'uploading' a bitstream, they depend on your setup.
For instance, with the mystorm board, which has a hardcore cpu as well, the bitstream is managed by the ha…
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libffi is not installed by default on MacOS Sierra:
dyld: Library not loaded: /usr/local/opt/libffi/lib/libffi.6.dylib
Referenced from: /Users/sonium/.apio/packages/toolchain-icestorm/bin/yosys
Rea…
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En el archivo patch-iCE40-HX8K.py faltaba la salida **D16**.
Lo adjunto con la corrección.
[patch-iCE40-HX8K.zip](https://github.com/FPGAwars/icestudio/files/629176/patch-iCE40-HX8K.zip)
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Hi,
In this repo are located the cross-compiling scripts for the [Icarus Verilog toolchain](http://iverilog.icarus.com/) used by [Apio](https://github.com/FPGAwars/apio):
https://github.com/FPGAwars…
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Hi,
In this repo are located the cross-compiling scripts for the [Icestorm toolchain](https://github.com/cliffordwolf/icestorm) used by [Apio](https://github.com/FPGAwars/apio):
https://github.com/F…
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Estoy trabajando con la placa **ICE40-HX8K** en Windows 8.1 con 64 bits, y no consigo que **Icestudio** detecte la placa. Instalé los drivers **libusbk**, como adjunto en una captura, pero no hay form…
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It would be great to have parcial implementation of the buses, only for connecting blocks.
Let's take this two blocks as an example, conected by a wire. It is done in icestudio like this:
![two-…