-
Hi,
I am currently working on getting the OpenRISC (or1k) architecture building and working again (mainly adding the address space). There is one undefined symbol `__cxa_atexit`, which seems to be …
-
Hello,
I'm trying to get the toolchain to compile, but I'm unable to grab Stefan's OR1k version of Linux.
The fetch step includes cloning a repo on openrisc.net, which no longer exists.
I haven…
-
It would be good for LiteX to generate suitable device tree for Linux / Zephyr (potentially micropython in future).
I started (but never finished) a tool to take a `csr.cvs` file and generate a [Li…
-
Third party integration in ETISS is a bit intransparent. A lot of libraries are copy-pasted into ETISS source code which is mostly fine, but makes is harder to maintain and differ what foreign code is…
-
@cr1901 hit this problem when getting set up.....
-
To be productive with optimsoc, not only the optimsoc documentation is necessary, but also the one for newlib, mor1kx, the or1k gcc extensions, GLIP, etc.
Idea: Rework the documentation section on …
-
LiteX supports multiple CPU architectures, lets try and support all of them!
-
I couldn't find pin assignment of JTAG_TAP for de0_nano from orpsoc-cores/systems/de0_nano/data/pinmap.tcl. Does that mean I couldn't use OpenOCD to write program to RAM via JTAG?
This seems to expla…
-
Main Rationale behind this is the copy/v86 project.
A number of Linux distros and some OSes can run OpenRISC, and it would make sense if:
- Have options to use different OSes that supports RISC
…
sr229 updated
5 years ago
-
LiteX supports lm32, mor1k, risc-v and soon sh2 CPU architectures. Currently the emulation assumes lm32 arch.
Qemu supports emulation of all these archs, so we should support using them.