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Bravo on experimenting with an open standard.
I'd love to see this work evolve into using more of CMSIS and eventually enable CMSIS & RISC-V to also benefit from it.
Are you in contact with anyb…
0Grit updated
2 years ago
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I am working on a HAL implementation for a UART peripheral and came cross odd behaviour:
```rs
...
if status_reader.rdavl().bit_is_set() {
let data = uart…
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When running the schema validator in \CMSIS\Utilities\CMSIS-SVD.xsd against the SVD file for our microcontroller, we find some errors. According to the documentation in https://arm-software.github.io/…
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https://github.com/rust-embedded/svd2rust/runs/3799394000?check_suite_focus=true
```
The following predefined values can be used:
registers
buffer
reserved.
```
https://www.ke…
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Every time starting debug, cortex-debug will download executable to mcu flash.
How start debugging without download?
my cortex-debug configuration:
```
"type": "cortex-debug",
"name": "…
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Currently the implementation is in a way that a device and its processors are described via: https://github.com/pyocd/cmsis-pack-manager/blob/main/rust/cmsis-pack/src/pdsc/device.rs#L169.
This essent…
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I'm working with a Renesas RA2E1 MCU, and it seems to be unusually picky about how its registers are accessed. Unfortunately, this causes problems attempting to use the Cortex Peripherals view: bytes …
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Due to the presence of the ``/``/`` tags, it appears that this SVD is targeting version 1.1 of the schema rather than 1.0 as currently reported in the SVD.
I used [xmllint](https://linux.die.net/ma…
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The bit set in RCC->AHB1 for crc enable is shifting (1
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The SVD generator at present assumes that all registers are a fixed width of 32 bits. This is not a correct assumption, however.
For example, in the `XTS_AES` peripheral, the `PLAIN_MEM` register s…