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Hi All,
Completed build project on Alveo U50, however when on run ./ping_fpga it always returns 192 of cmac stat_rx_status, no matter how many time I try to test, thus the link never become ready,…
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Hey all,
I built the project from source on a ubuntu machine as recommended in the documentation (built without CUDA as there are no capable cards in the machine). The machine has an alveo u250+alv…
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I have ALVEO U280 connected with my system. I am able to launch kernels on U280 with opencl. But I am trying to work with PYNQ overlays. But PYNQ doesnot detect devices.
import pynq
pynq.Device.de…
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According to your paper on [arXiv](https://arxiv.org/pdf/2301.00290), it seems that:
- You used Vivado 2021.1.
- Implemented BARVINN on a Alveo U250.
As far as I understand, this repository has b…
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Hi,
I want to test tensorflow 2 for Alveo U200 and I want to start with a pre built model. Unfortunately the .xmodel file is missing for alveo U200 under tensorflow 2 in the .ymal file. Can someone …
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Hi,
I came across your design as I am looking for a Ethernet design with UDP listener to be implemented on FPGA. I have a Alveo u50 card installed in my machine. I was able to generate the bitstrea…
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https://github.com/Xilinx/Vitis-Tutorials/blob/2022.1/Hardware_Acceleration/Introduction/guided_sw_examples.md
The tutorial does not take care of Vitis_Libraries and the flow is failing with below…
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** Which tutorial are you running? **
https://github.com/Xilinx/Vitis-Tutorials/tree/2022.2/Hardware_Acceleration/Design_Tutorials/10-get_moving_with_alveo
** Describe the issue **
It fails on sw…
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Hi
I was trying to go thru the 09-Ethernet-Alveo using LANE=4
However, vitis was not able to complete the implementation and leaving an error of below
[Constraints 18-1000] Routing results ve…