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There are a few places in the code-base where `FEATURE_HW_INTRINSICS` functionality is dependent on `FEATURE_SIMD` also being defined.
The hardware intrinsics feature should (ideally) share code wi…
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128-bit SIMD.js leverages a broad convergence across architectures. SSE through SSE4.2, NEON, Altivec, MSA, all largely lined up at 128-bit SIMD registers, mostly IEEE-754, a lot of commonality in the…
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We've iteratively exposed support for various levels of hardware intrinsics since .NET Core 3.1. In .NET 7, we exposed the new "cross platform" hardware intrinsics which aim to help simplify the writi…
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Any plans to introduce async methods to ExcelPackage such as:
```csharp
public async Task SaveAsync();
```
Thanks
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Increasingly we are taking changes that use hardware intrinsics to accelerate parts of CoreFX. Without special care, our testing will only ever cover the AVX2 (or AVX) path, not the software path and …
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The CMPXCHG16B instruction is required to do CAS or atomic read of 128-bits values in memory. Currently, atomic 64-bits read and CAS is supported on .NET with the `Interlocked.CompareExchange` and `In…
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## 🚀 Feature
Universal binaries (x86_64+arm) made available on pytorch.org for the libtorch library on mac.
## Motivation
C++ applications requires libtorch to run PyTorch models saved as torch…
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# Baremetal RISC-V Renode - Part 1: Blinky - y2kbugger
[https://blog.y2kbugger.com/baremetal-riscv-renode-1.html](https://blog.y2kbugger.com/baremetal-riscv-renode-1.html)
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As new instructions have been added for SSE and AVX, the existing encoding tables aren't adequately expressive, resulting in a great deal of conditional code that impacts throughput. This should be re…
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This happens on xamarin-android/main (.NET8), but I suppose it will apply to other platforms as well.
I noticed that `System.Private.CoreLib.dll` output by the linker for arm64 RID contains X86 and…