-
The reconfigurable phase-locked-loops on the Cyclone 3 are slightly different to those on the stratix 3 that this design has been ported from. The mod_homodyne_c3, pll_control_c3_full and pll_reconfi…
-
I run the command: modeltest-gui
I got modeltest-gui: command not found
after finished installing modeltest-ng
![Screenshot 2024-07-23 151649](https://github.com/user-attachments/assets/fc0e0680…
-
**Is your feature request related to a problem? Please describe!**
The pitch detection PLL builtin to Treemonster could use some expansion.
**Describe the solution you'd like:**
PLLs are inherent…
-
USB stdio fails if SYS_CLK_KHZ overridden to 32MHz (PLL_SYS_VCO_FREQ_KHZ and PLL_SYS_POSTDIV1, 2 are also set to valid values).
/dev/ttyACM0 does not even appear
dmesg shows errors:
usb 1-7.2: ne…
-
Hello Sasha.
I don't know this platform very well. Maybe I'm posting in the wrong place. I have a question. Sorry again, I guess I'm in the wrong place. Referring to your explanation https://github.c…
-
The goal of this issue is to document the kinds of PLL primitives of the various FPGA manufacturers, so that we can support them in nmigen.
---
## Lattice
Lattice PLLs are different for the dif…
-
I wanted my Pico 2’s default architecture to be risc-v, so set CRIT1_BOOT_ARCH (`picotool opt set crit1.boot_arch 1`).
The chip now runs at one third the nominal rate (50 MHz instead of 150).
-
## Prerequisites
- [x] This is not a usage question (Those should be directed to the [community supported forum](https://wordpress.org/support/plugin/polylang), unless this is a question about …
-
Hi,
as I would like to use hsdaoh for MISRC the questions is: Is libhsdaoh going to be a general-purpose library designed for handling the data produced by the hsdaoh FPGA code and interfacing the HD…
-
After I update from SDK 2.0 to 2.1 I got this error when ESP wakes up from deep sleep and try to connect WiFi.