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Needs to include packet capture, key GPU kernels, basic output networking, and a simple receiver config with validation steps.
Main BX-engine config file components:
Input networking:
- [ ] Packet c…
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the main board
![obraz](https://user-images.githubusercontent.com/4325054/193119276-6ff5ae9d-1dc5-4aa9-80b0-d1a1907951a8.png)
the debugging mezzanine
![obraz](https://user-images.githubuserconte…
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Hi @rodolfocarobene,
I am trying to run a Rabi in 2 qubits at the same time and I get this error
```
[Qibo 0.2.8|INFO|2024-07-24 07:32:42]: Loading platform /home/users/javier.serrano/lab/qibol…
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Thank you for this great starting point for MTS designs.
I set up this project on a fresh SD card image (Pynq 3.0.1) for my RFSoC4x2 board, and followed the install instruction.
After power-cycl…
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I am trying to copy qick tool in RF SoC 4x2 board using pscp with folloiwng on windows terminal
D:\QICK\cloned_repo>pscp -r qick xilinx@192.168.1.58:/home/xilinx/jupyter_notebooks/.
but everytime I…
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The system will halt on initialisation if the system is not connected in loopback. A kernel interrupt is required to fix the issue.
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Hi, when we use the frequency planner, the harmonics 1 or 2 has the most noticeable power and affect the final performance, should we reorder the yaxis to rank the harmonics No. from smaller values to…
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On latest master (a2fbcb8bfd64d5d97ba37b16b501aa99a0fb3bfb) this causes an assertion error in artiq_ir_generator:
```python
from artiq.experiment import *
import numpy as np
class TestInt64Ind…
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Hi ikwzm
I'm using u-dma-buf (master branch)on a Zynq MPSoC Ultrascale+ board (ZCU111),and I use xilinx offer petalinux bsp for zcu111 with the petalinux version is 2020.2.
I compile u-dma-buf.c a…
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Thank you for making this repo available. I wonder if you could share prebuilt bitstream and image for us to try.