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I have a Xilinx Zynq and I would like to move this project on it, however, I wonder the requirements of platform-specifically files...
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In the CHaiDNN documents tells that it support Power Layer but none of the implemented models is having PowerLayer support. This has been checked by i was trying to use the Googlenet model and our app…
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Hi all, I want to build ChaiDNN for ZCU106 using SDx 2018.2, but something gets wrong as below:
14:15:41] Starting logic placement..
[14:16:01] Phase 1 Placer Initialization
[14:16:01] Phase 1.1 Pl…
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hey @dhm2013724 thank you for uploading your code. as you said this runs at a speed of 1fps on pynq ryt? do u think that it is possible to make it run on pynq real time with tiny-yolo (if you further …
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It appears we don't have any examples / demos which run on Zynq parts at the moment?
I don't know which board should be targeted?
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Hi!
As I understand the benchmark example program should also work for a VDMA engine looped back, correct? I have a design which contains only a VDMA engine with TX and RX looped back. The module l…
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http://www.elecfans.com/emb/fpga/20171118581789_a.html
http://m.elecfans.com/article/973606.html
https://reborn.blog.csdn.net/article/details/84977359
- 官方:Vivado Design Suite Tcl Command Reference…
cisen updated
2 years ago
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So far we have 2 working modes -- one for LHC trigger (low reuse factor, 1-6, weights in the fabric) and one for "naive" serial mode (see PR #45).
One interesting mode is a very large reuse facto…
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Hello, when I make the Makefile in the ' cpp/accel/sdsoc_build ' , errors about the SDSoC license occurs.
![image](https://user-images.githubusercontent.com/28952216/39615064-a360bdae-4fa6-11e8-93f0-…
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Hi,
Can you please share how to run ChaiDNN using Vitis tool? Vitis includes the functionality which was supported by SDSoc. Do I need to make significant changes in the code?
Regards,
Nivedi…