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Hi, everyone.
I recently ported keystone to HiFive Unmatched in the course of my work.
Using the buildroot system, SD card image that work with Unmatched can be created with a single `make` comman…
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Hi everyone, I am a newbie in Chisel.
Does anyone has experience in that case, please help me?
Thank you so much for any kind helps.
My goal is to add a instruction detecting signal (in particula…
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After compiling and running coremark for the HiFive1 RevB, I get unexpected results as far as the clock speed as calculated from the provided data.
Results:
```
2K performance run parameters for co…
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I'm not sure exactly what's going on here, but if I set `RISCV_PATH` but don't have a compiler in `PATH` then the run of `configure` in `freedom-metal` doesn't pick up the target GCC.
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Building metal does `mtvt` CSR operations, and since that's a CLIC thing it's not part of the upstream GCC port. We should just fall back to a register number if possible, but if we're using all the …
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I am using a [bootlin](https://toolchains.bootlin.com/) RISC-V toolchain (GCC 10.2.0, binutils 2.34) to build second boot.
First of all, this toolchain does not support nano specs, and I had to do …
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The debug spec provides for an idle count to be used after every dm access.
This is read into info->dtmcontrol_idle.
This is never used; it presumably should be a baseline for idle_count in risc…
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Hi, I link to here due to riscv-qemu
in the riscv-qemu's README, they used **priv-1.9 branch of riscv-linux** as an example for building linux image for riscv-qemu
However, there is no priv-1.9 bran…
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Both of the following fail on master:
```
make -f Makefile.veraiofpga verilog
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We determined to port a complete runtime environment including OpenJDK11 + OpenJ9 + OMR (without JIT) to the RISC-V development board (e.g. HiFive Unleashed with Linux support / please refer to https:…