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Hello,
I found `clash` translates `b = replicate d4 a` into a kind of code like the following:
```systemverilog
logic [1:0] a;
logic [1:0] b [0:3]; // unpacked array
assign y = '{4 {x}};
…
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Hi, I wanted to ask few questions about the moore-vhdl-syntax. I would really appreciate if you answer.
1. What is the current status?
2. How many of the constructs defined in the LRM is it able t…
m-kru updated
3 years ago
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I would like to compile my SV code with yosys+UHDM, I followed the instructions from here:
https://antmicro.com/blog/2022/02/simplifying-open-source-sv-synthesis-with-the-yosys-uhdm-plugin/
except I…
jeras updated
2 years ago
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In `VpiSignalObjHdl::initialise`, this is causing Active-HDL 10.1 to segfault:
https://github.com/cocotb/cocotb/blob/9a850f9774301e319786db4d24592742f859cdfd/cocotb/share/lib/vpi/VpiCbHdl.cpp#L246
…
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The parser is failing when a logic is called 'inf':
test2.sv:5:13: syntax error, rejected "inf" (syntax-error).
Short summary.
verible-verilog-lint test2.sv
```systemverilog
module fred…
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Our simulator makefiles get the list of Verilog and VHDL sources in separate variables, and in ``Makefile.questa``, ``Makefile.aldec``, ``Makefile.activehdl``, there are separate compiler calls to com…
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[VUnit](http://vunit.github.io/index.html) is an open source unit testing framework for VHDL and SystemVerilog proving the functionality needed to realize continuous and automated testing of your HDL …
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We are at the verge of reaching 50,000 downloads in the marketplace. From this point, I feel it is good to have a structured development plan. The following are a few ideas that I have.
## 1. Suppo…
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Can you add support for the register description language SystemRDL?
Here is a link to the standard https://www.accellera.org/downloads/standards/systemrdl.
There is also a great open-source commu…