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The MOSFET model has behaves as though it doesn't have a body diode - in effect allowing the MOSFET to block current in both directions between Source and Drain. All real MOSFETs have a parasitic dio…
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## Expected Behavior
Tapcells have class CORE and should be CORE WELLTAP which is a LEF 5.6 construct and the LEF is 5.5
The script that prepares the LEF files from magic, which would need some ad…
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**Submitting author:** @miketuri (Michael Turi)
**Repository:** https://bitbucket.org/miketuri/perl-spice-sim-seus/
**Version:** v1.0.0
**Editor:** @VivianePons
**Reviewers:** @mzszym, @victorvalgenti…
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Is there a corresponding reference or documentation?
There are mainly the following doubts: 1. The purpose of the shift signal and why it is directly equal to y. 2. Is the overall implementation of …
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Defect Description
In the Quizzes section of Design Of Digital Circuits Using Verilog experiment in VLSI lab, the questions are not ported properly. Given a link that redirects to vlabs VLSI quizzes …
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Defect Description :
In the experiment section of Design Of Digital Circuits Using Verilog experiment, Instead of porting the experiment using iframe tool, ported the experiment using text editor in …
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My goal is to run a simple C++ Hello world program on google app engine via Docker deployment.
I'm doing this via terminal where i'm following this guide: https://cloud.google.com/appengine/docs/f…
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So, Firrtl seems to have "Info" fields. Is there some existing way to tag additional info at the Chisel level to have it accessible in Firrtl?
My particular scenario (pertaining to memories):
If req…
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With 726bfd5 I get this (after `python setup.py develop --user` and python 2.7.5):
```
matej@mitmanek: examples (master)$ ls
bibtex.py citeproc_json.py xampl.bib
matej@mitmanek: examples (master)$ …
mcepl updated
9 years ago
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Dear Marco,
I am adding this issue as a placeholder for implementing the inproceedings entry type. (I know you did not initially plan to implement this.) If I have some bandwidth next weekend, perhap…