-
```
What steps will reproduce the problem?
1. Watching IPTV in Lithuania.
2. Enabling vpi/vci for each individual port.
What is the expected output? What do you see instead?
Internet and IPTV at the …
-
Hi,
Is there any chance of uploading the VPI source code in the hardware simulator: [https://github.com/intel/FPGA-Devcloud/tree/master/main/HandsFree/Simulator/DESim](url)
We would like to mak…
-
```
What steps will reproduce the problem?
1. Watching IPTV in Lithuania.
2. Enabling vpi/vci for each individual port.
What is the expected output? What do you see instead?
Internet and IPTV at the …
-
- Utilize VPI's workflows in other repos
- Reduce duplication
- Simpler to manage across many repos
-
Hello,
in an effort to improve the support of force/release in cocotb, I was surprised to discover that Verilator v4.218 exposes the ``__VforceEn``, ``__VforceVal`` signals in the VPI interface but V…
-
I'm trying to make a checkpoint module to dump and load simulation state. Looping over simulator objects results in a WARNING if an always block has a name, like this:
```
always @(posedge clk) be…
-
Discussion of proposed solution following #1611. #1060 likely related.
### Background
After waiting on an edge trigger on a signal, we exist in a state where computations based on the change in va…
-
My server environment will use connectx-7 vpi and intel 810-XXV nic card. So i need to register intel nic into rdma resource pool.
Is it possible to use intel nic? If so, could you provide config.map…
-
Hello,
I am following this tutorial: https://nvidia-isaac-ros.github.io/repositories_and_packages/isaac_ros_argus_camera/isaac_ros_argus_camera/index.html#stereo-camera
I am having a problem wit…
-
The mess of `gpi_cb_state_t`, `handle_xxx_callback`, `cleanup_callback` and `set_call_state` could potentially be massively simplified by removing the whole thing.
I think this was originally added…