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Hi there,
I would like to use the code from branch new-devices to program a ZC706 board, but as others have noticed, the icenet submodule is private. Would it be possible to make it public?
I ju…
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I'm working on getting Rocket and Boom running in a quadcore configuration each on ZC706.
The master branch of fpga-zynq is rather stale (nearly a year behind) and development of the other projects…
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I want to synthesize rocket-chip with BOOM cores on zedboard, but I can't find how to do that.
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I am executing a **$ make Sim** command.but i got error like this **bootconsole [early0] disabled
** .
Can any one please give me solution for this
/home/billa/Sifive/freedom-u-sdk/work/riscv-is…
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I've seen this example:
https://github.com/riscv/riscv-asm-manual/blob/master/riscv-asm.md#constants
Whether the function of "puts" here is displaying string "Hello World\n"?I tried to build the p…
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**_Reported by Andrew Boie:_**
We introduced an SOC configuration for the SiFive Freedom E310 SOC. However there are no boards defined under boards/riscv32 which select this SOC configuration and thi…
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freedom commit id cd9a525a662b9eaf27c14533159d723efcf4c184
freedom-u-sdk commit id 62ae153449574c6d9a9f83510e735ef632a3ef8b
vivado 2016.4
Nothing went wrong during compilation. But when I boot linu…
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There are two targets in simulation (freedom-e300-sim and freedom-u500-sim) https://github.com/riscv/riscv-tests/tree/master/debug
**What about testing debug for default rocket chip in simulation?…
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Hi Does sifive have a plan to port uboot for freedom u540 or riscv-qemu ?
AndesTech summit thier patch for their n{x}25 cpus. [U-boot link](http://git.denx.de/?p=u-boot.git&a=search&h=HEAD&st=commi…
xfguo updated
6 years ago
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Hi
Im was trying to get a 32bit version of Linux running on spike for quite some time now.
Its quite hard to find much documentation on RISCV 32bit that works for the current version. In many…