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If I understand the code correctly, the current IDMA implementation seems to overflow if you are not emptying the buffer, even though you are reading all the data. For example, if your buffer is 4 byt…
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Context:
- RK3588 support multi-core encoding for spliting (`HAVE_VEPU2_JPEG`)
- partions_group allocation uses `MPP_BUFFER_TYPE_DMA_HEAP` on hal_jpege_vepu2 task execution
- dma heap is not enabl…
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In normal I/O, if you wanted to make sure your data structure is aligned on some large boundary (e.g. 8 MiB) but you wanted to do smaller writes, you would simply write out how much data you have (ali…
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The flipDMABuffer works very well (as in keeping the display clean) but comes at a cost of really dropping the fps. Is this because of has to wait for the display to complete one full DMA output cycle…
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In #326 we started discussing how to avoid having to pass in DMA buffers to low level drivers.
### The Problem
When transferring data to a peripheral with the DMA, the data is transferred directly…
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### Answers checklist.
- [X] I have read the documentation [ESP-IDF Programming Guide](https://docs.espressif.com/projects/esp-idf/en/latest/) and the issue is not addressed there.
- [X] I have up…
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I am using the latest release with a Radxa Zero 3W and for my use case I do need smooth video playback.
Currently video playback is not gpu accelerated (no mali acceleration):
When starting chromi…
faken updated
4 months ago
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We ignore unknown control bit 4, needs research.
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### Failing/Disabled Tests
- [ ] ESP32-C3/ESP32-C2: `uart::test_send_receive_different_baud_rates_and_clock_sources`
When using the `RcFast` clock source, the code just hangs in https://github…
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Hello , I have a custom board based on the MAX32650 . UART2 is connected to a FT230X chip and is working fine . In the examples , data is looped back from UART2 to UART1 . I modified the …