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From experience trying to explain our lowerin in the paper and presentations, it seems that we have too many dialects to explain what's going on. I propose to move the riscv-specific operations to two…
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Expression of hexadecimal immediates in RiscV assembly is unclear. If we explain or demonstrate correct behavior [here](https://docs.opentitan.org/doc/rm/asm_coding_style/) it will guide fixing issues…
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For a full list see, for example, https://riscv.org/wp-content/uploads/2017/05/riscv-spec-v2.2.pdf, pages 110 and 111.
Currently some RISC-V assembly pseudo-instructions appearing in assembly outpu…
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https://github.com/powdr-labs/powdr/pull/678 adds the Poseidon submachine to the RISCV machine and a bunch of extra registers. This can be quite costly for cases that actually don't use Poseidon at al…
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When I use riscv-nulei-elf-gcc to assemble the mrmuldv,compiler does not recognize instructions and syntax in assembly code.
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Hi,
I have some custom instructions based on vector registers, and I want toolchain to support them. So far, I have been implemented them in binutils, and they works fine, but I get stuck when addin…
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### Technical Group
Unprivileged Spec IC
### ratification-pkg
Zvfh/Zvfhmin
### Technical Liaison
Andrew Waterman
### Task Category
Arch Tests
### Task Sub Category
- [ ] gcc
- [ ] binutils
- …
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# Baremetal RISC-V Renode - Part 4: KOS Context Switch - blog.y2kbugger.com
[https://blog.y2kbugger.com/drafts/baremetal-riscv-renode-5.html](https://blog.y2kbugger.com/drafts/baremetal-riscv-renod…
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The meaning of the relocations' operands in the Details column is not documented. Presumably `S` stands for symbol and `A` for addend. But maybe I'm interpreting it incorrectly as something seems to b…