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Hi, I generated a verilog module for the litedram core and now I want to simulate it as as ASIC design, basically I am trying to dummy out those interfaces with FPGA.
Existed bench are all FPGA bas…
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#### Description
#### Steps to reproduce the issue:
1. Perform fast/warm-reboot
Observe that after ```create_switch()``` SAI discovery process runs and takes (in this case 1.02 sec):
`…
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- [x] LD1 should to be driven by transistor
- [x] consider connecting LDOs feedback to connector instead of one power pin.
- [x] change PCB name from "pcb"
- [x] add outjob file
- [x] add keep-o…
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Hi,
From what I understand Blake2b and then Blake3 were designed with the modern CPUs in mind, and BLAKE3 is currently the fastest secure hash function in modern CPUs.
I wonder how would they comp…
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As every other FPGA engineer in the world I am frustrated at the compile times of my tools. I see in one your papers, you mention that you use icc2 from synplify. I also see here that all you need is …
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To whom it may concern,
We are from Microelectronics Research Lab (MERL), based in Pakistan working on developing RISC-V based ASICs and SoCs.
Currently we were working on developing an Indigeno…
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We are looking into DentOS for a line of OpenVPX switching products that contain both a Mellanox Spectrum switching plane (already supported by dentos) as well as a Marvell Aldrin2 100g (98DX8525). I…
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**Description**
In sonic 202012, we are observing that COPP TABLE entries are removed from APP_DB by https://github.com/Azure/sonic-utilities/blob/2a982a1fe084b334fb99c372d171273931a0851b/scripts/…
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Found this out while toying with the BM1387;
The asics do not search the entire nonce range. My 2 asic miner splits the 32-bit range to 0x00000000-0x80000000 for the first asic and 0x800000000xffffff…
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Hello,
**Type of issue**: bug report
**Impact**: API addition (no impact on existing code)
**Other information**
When SyncReadMem is created with ReadFirst or WriteFirst specified SyncReadMe…