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I am not sure if my understanding is correct.
I have checked the data in the gzip.inbound, and the head data are
0x400000000a000400 SoT 0xff
0x0000000000000000 EoT 0xff
0x800000000a00…
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Hi, I generated a verilog module for the litedram core and now I want to simulate it as as ASIC design, basically I am trying to dummy out those interfaces with FPGA.
Existed bench are all FPGA bas…
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This was mentioned by @dpetrisko.
Apparently Vivado is failing to map wide FMAs to DSPs efficiently.
Lakeroad alone probably can't do this -- once a solver query needs to figure out that some co…
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To whom it may concern,
We are from Microelectronics Research Lab (MERL), based in Pakistan working on developing RISC-V based ASICs and SoCs.
Currently we were working on developing an Indigeno…
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# tl;dr
1. `summary.py` can't find the antenna report (`*antenna.rpt`) because I think it's now in a different path:
* **I think the actual file it might need is `log/signoff/*antenna.log`**
…
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Hello,
We find this WaveDrom very useful in FPGA/ASIC design flow especially for RTL designers. I am exploring adding support to extract a UVM test from a given WD file. We have a simple UVM test l…
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**Memory** is not SRAM only, they should also include, SRAM, ROM, RF
**Type of issue**: Feature Request
**Is your feature request related to a problem? Please describe.**
Chisel is using behavi…
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#### Description
#### Steps to reproduce the issue:
1. Perform fast/warm-reboot
Observe that after ```create_switch()``` SAI discovery process runs and takes (in this case 1.02 sec):
`…
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**Description**
**Steps to reproduce the issue:**
1. Deploy the 202211 image, and load the config with minigraph
2. execute the log analyzer.
3.
**Describe the results you received:*…
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where can I find the verilog versions of the ztachip as Iam not familiar with the VHDL