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│⋮ 0x00003dca 7eba rev16 r6,r7
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Its easier to read. just keep the old naming for compat for about a year, and then we can deprecate them
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Currently the UX of it is far from good, in my opinion. Would be nice to rethink the interface.
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## Description
When analyzing code that uses [AVX, AVX2 or AVX512](https://en.wikipedia.org/wiki/Advanced_Vector_Extensions) vector instructions, Radare2 does not generate ESIL for those instructio…
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Now that we have esil, a cleaner way to emulate and debug bf would be esil. so maybe we no longer need bfdbg
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Currently Xtensa support is pretty basic and is based on the binutils code.
- [ ] Implement Xtensa in Capstone: https://github.com/capstone-engine/capstone/issues/2015
- [ ] Port Xtensa plugin to …
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more and more common programs are using SIMD instructions lately, because of gcc optimizations. so it is important to support that
- [ ] MMX (x86)
- [ ] SSE (x86)
- [ ] AVX (x86)
- [ ] NEON (arm)
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Instructions with conditional blocks don't have an unconditional edge from the `true` block to the next instruction. This leads to adding an edge to the exit block which ruins all analysis!
Example…
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- [x] Disassembly support
- [x] File format support
- [ ] Analysis plugin
- [ ] Emulation with ESIL
- [ ] Assembly support
- [ ] Regression tests
- [ ] Documentation
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aeim does not honor information from ````im```` . This sucks, now I have a working io-implementation and a broken esil-memory allocation :/