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Intel SHA instructions assist with hardware acceleration of the SHA-1 and SHA-256 hash algorithms.
Current Ryzen processors that support these instructions can reach SHA-256 speeds of around 2 GB/s…
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`ConditionalSelect_ZeroOp_mask` test for `AddSaturate` fails with internal error.
**Execution steps**:
```
DOTNET_TieredCompilation=0 $CORE_ROOT/corerun ./artifacts/tests/coreclr/linux.arm64.Ch…
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Run-time simd checks can be beneficial in long-running cases (`SpanHelpers.SequenceEqual` for example)
# Run-time simd checks can hurt performance because of redundant checks...
Could it be fixed? E…
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Hi everyone,
I´m trying to implement the [EDIFACT VERMAS D16B](https://www.truugo.com/edifact/d16b/vermas/), and I´m having a hard time understanding/using `SegmentGroup`.
![image](https://us…
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### Description
The following example:
```csharp
class Program
{
static int Square(bool res) {
if (res)
return 9;
return 5;
}
public static vo…
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### Background and motivation
`VPCLMULQDQ` is supported by Intel in the Ice Lake and newer architectures, and by AMD in Zen 4. It allows for parallel `pclmulqdq` in `Vector256` and `Vector512` and …
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Compiling anything with `--instruction-set:base,sse,sse2,sse3,ssse3,sse4.1,sse4.2,avx,avx2,avx512f,avx512bw,avx512cd,avx512dq,avx512vbmi,aes,bmi,bmi2,fma,lzcnt,pclmul,popcnt` hits an assert in both il…
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**Failed in:** [runtime-coreclr jitstress 20240821.1](https://dev.azure.com/dnceng-public/public/_build/results?buildId=784551&view=ms.vss-test-web.build-test-results-tab&runId=20141776&resultId=11847…
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When a test fails, and you view the Error Message in Azure DevOps, you get something like this:
```
\ncmdLine:/private/tmp/helix/working/B08009A5/w/A2FA08B1/e/Interop/ICustomMarshaler/Primitives/ICu…
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This issue describes planned improvements to Intel architecture (x86, x64) ISA support for .NET 9.
In .NET 8, AVX-512 ISA support was added (see https://github.com/dotnet/runtime/issues/77034). In …