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Hello
In Espressifn ESP32 doc (http://esp-idf.readthedocs.io/en/latest/api-guides/jtag-debugging/configure-other-jtag.html) , Jtag adapter must be connected to GPIO12, GPIO13, GPIO 14 and GPIO15 ES…
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I'm using it to drive a JTAG port and the speed of it is much slower that I expected. Is there any way to improve performance? It is running the JTAG clock at 3MHz, but the overall communications sp…
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**Describe the bug**
I'm trying to debug an in-house RISC-V core via JTAG, using the generic "riscv" chip setting. `probe-rs info...` does not work for me, looking at the logs it seems it's using the…
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### Expected behavior
Currently, to send a data fragment larger than 256 bytes via CONSOLE_USB_SERIAL_JTAG, a forced insertion of `\n` between 256-byte fragments is required.
I would like the beha…
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Hi,
I was wondering if there are any plans for other FPGA ports. I'd mostly be interested in Zedboard and ZCU102.
In the past these ports (and softcores as standalone projects in general) have bee…
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The `LicheeRV Nano 70405 Pin Definition` (the pinout diagram of the board) specifies the following functions for pins `A18` and `A19`
- A19: GPIOA_19 UART1_RX JTAG_TCK PWM_7
- A18: GPIOA_18 UART1_TX…
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~~I don't own an [STK600 board](https://www.microchip.com/en-us/development-tool/ATSTK600), so I can't confirm this.
But from the looks of it, the STK600 can only be used in ISP, HVPP or HVSP mode w…
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Hello. Trying to use your program to flash / dump external flash **25Q64** on custom board with **GW2A-LV18EQ144C8** FPGA part in LQ144 package. The reading seems to work fine at first look. But I`m u…
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Using either `sipeed-rv-debugger` or `jlink` (J-Link EDU Mini in my case) as _upload_protocol_, it fails with the following log on a Sipeed Longan Nano:
```
Open On-Chip Debugger 0.10.0+dev-00911-gc…
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Hello,
For a hobby project , I need to access the JTAG data by communicating the JTAG server to program a MAX10 FPGA, could you please suggest some solutions/hint to do it.
Thankyou.