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Over the last week I finally found enough time to test Memtest86+ on several more "legacy" AMD platforms that I have: AM3+/FM2+/AM1 (FS1b)/FS1.
To be more specific, the following CPUs were tested:…
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Below is the output of `pcm`.
```
Intel(r) Performance Counter Monitor ($Format:%ci ID=%h$)
===== Processor information =====
Hybrid processor : no
IBRS and IBPB supported : yes
…
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When I managed to integrate `zpoline` into our system, it can not mprotect `zero page` as execute-only, even if I changed the `mmap_min_addr` successfully.
```bash
$ LIBZPHOOK=libzphook_basic.so L…
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Something to note, i am running linux on a macbook.
Throttled version: `throttled-git-r306.4b076e1-1`
CPU: i5-1038NG7
`systemctl status` output:
```
Feb 25 01:22:51 FutureEndeavours systemd[1]:…
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# MSR 2014 Chunk 3
### Table of Contents:
http://dl.acm.org/citation.cfm?id=2597073&preflayout=flat#prox
### Papers:
pg. 300-363
First: Classifying unstructured data into natural language text and t…
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on linux RBM does not enable MSR because the xmrig isn't started with root privileges:
` * ABOUT XMRig/6.21.0 gcc/7.5.0 (built for Linux x86-64, 64 bit)
* COMPILED BY RainbowMiner https:/…
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I want to get the values for L1, L2, L3 cache miss counters, Is that possible to do so using `readmsr`? If yes where i can find list of addresses of all register i can get get value for?
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HI~
Thanks for your work~ When I tried to reproduce the result on the MSRS dataset, I got a different performance compared with yours. Here are my results.
```
Your Min…
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MSR 0x150 writes seem to be blocked by the BIOS, is this something you could allow?
It's necessary for undervolting, using https://github.com/georgewhewell/undervolt
I'd specifically like to use …
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https://www.phoronix.com/scan.php?page=news_item&px=Linux-Filter-Tightening-MSRs
Maybe it's worth to collaborate with upstream somehow?