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i build and install xrt_2019.2 on ubuntu 18.04,
(1) lspci -vvv -d 10ee:
xclmgmt and xocl kernel driver can be recognized
(2) sudo /opt/xilinx/xrt/bin/xbmgmt flash --scan
Flashab…
crizy updated
2 years ago
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Hello there,
I currently am experimenting RandomForests from sklearn into a ZCU102 board. I first tried with the classic HLS/Vivado/Vitis flow but was struggling with the results. I tried using py…
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![image](https://github.com/user-attachments/assets/2c99cd69-031e-4964-9461-405999841a6a)
Why am I seeing this?
Also when I tried to login it showed this:
![image](https://github.com/user-attac…
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Hello. I'm getting an output model.c file with 230mb in size. I set the input ONNX file from yolov7-tiny.
the issue is when i want to load model.c in my IDE as it throws segmentation error in compili…
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When I use 'pip install -v -e .' to package my code (which depends on pytorch-nndct),errors like below
```
File "/home/zq/anaconda3/envs/sxcv/lib/python3.7/site-packages/pkg_resources/__init__…
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![image](https://user-images.githubusercontent.com/5336511/178953608-8b7daea7-90e2-4006-8590-2f91df807f8e.png)
Using Vitis 2021.2 to compile to Vivado IP then using this in a Petalinux build.
S…
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Initially posted on Xilinx forums [1]: there is DMA cache incoherencies when using lwIP and the PS EMAC on a Zynq at high throughput. The problem can be reproduced by following the steps in described …
mpv89 updated
3 years ago
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Hi! Thank you for this resource! :) What exact annotation versions from the other species were used in creating and analyzing this annotation? The paper mentions Arabidopsis thaliana, Prunus persica, …
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3 KEY videos:
1) Creating custom AXI interface Slave part I: https://www.youtube.com/watch?v=meQcwzC4Vtk
2) Creating custom AXI interface Slave part II: https://www.youtube.com/watch?v=Vs0h0kue7…
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I'm getting following error when trying to start debugging, right after load command. Seems like there is an issue with stack unwiding.
/proj/sdk/gnu/microblaze/builds/HEAD/nightly/2017_11_15/rdi_…