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I have tried to run simulation for riscv_usb using $make sim
But will get following error.
iverilog -Wall -DSIM=1 -DBOARD_ICEBREAKER=1 -o /data/local/Desktop/USB_2019/RISC_V/ice40-playground/project…
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**Issue by [mithro](https://github.com/mithro)**
_Thursday Jun 06, 2019 at 23:26 GMT_
_Originally opened as https://github.com/m-labs/nmigen/issues/92_
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How do you suggest adding support for us…
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==> Upgrading twam/openfpga/nextpnr --without-gui --without-arch-ecp5
==> Downloading https://github.com/YosysHQ/nextpnr/archive/c9ba65e7b2364147f8b27fbff1bb85a961f665c4.tar.gz
Already downloaded: /…
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FXMA108 gives us ESD protection on all I/O pins. However, what about the ADC and the LDO? In particular, the turned off LDO has the output in hi-Z state, which seems like it might have bad implication…
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"FPGA assembly" (.fasm file) as its currently called, refers to an end user issuing low level instructions in a human readable text format to configure FPGA interconnect and logic elements such as FFs…
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I attempted to build the current HEAD on branch master (commit 628e60a), but it fails with an error:
```sh
openfpga/build $ cmake ..
-- The C compiler identification is GNU 7.3.0
-- The CXX comp…
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I'm trying to create a very simple example of using blockram on an iCE40. My code is [in this gist](https://gist.github.com/guanix/86e1dcaa0e16cd867270). yosys runs fine, but arachne-pnr gives this ou…
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https://github.com/azonenberg/openfpga/commit/7d634ccc5ba53d9fdf1110ecef8276a568e2ed59
Need to investigate wtf is happening, looks pretty innocuous to me?
OOMs on 1.18, 1.20, and 1.22 nightly
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HI
I'm trying to port your scope to ULX3S board, Goran sent me
your message to fix constraints and toplevel so I did that and
even more
I have prepared toplevel and constraints to build and I…
emard updated
5 years ago
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```
$ cmake --version
cmake version 3.9.3
CMake suite maintained and supported by Kitware (kitware.com/cmake).
```
I'm not sure what changed, but the build system is once again failing to fai…