@jmizrahi from #33:
On page 10, the SYNCOUT lines are not connected. Don't these signals need to be sent back to the FPGA as part of the communication protocol, and to enable deterministic latency?
@g…
I get the following error when building ProgSisComun/general/schedule/groups-71-72:
``````
[groups-71-72]$ adagio
++ ...af/asignaturas/2011-12/gtps/ada/ProgSisComun/general/schedule/groups-71-72
BB x…