-
crashing in the first SIMD test with:
```
(gdb) x/16i $pc-32
0x3ff7fd7ecc: addi t1,t1,1
0x3ff7fd7ed0: slli t1,t1,0xc
0x3ff7fd7ed4: xori t1,t1,-320
0x3ff7fd7ed8: vse32.v v29,(t1)
…
-
chunkset_neon.c **YES**
chunkset_sse.c **YES**
chunkset_rvv.c **NO**
Why chunkset_rvv.c is skipped? Any future work about it?
And the rvv implementation is based on which draft version?
-
As we know. 😊
RVV (RISC-V Vector) is a vector processing extension for the RISC-V instruction set architecture (ISA). It's designed to provide high-performance computing capabilities for applicatio…
-
# Summary
|New Failures|gcc|g++|gfortran|Previous Hash|
|---|---|---|---|---|
|linux: rv64gcv_zvl1024b lp64d medlow multilib |428/57|0/0|0/0|[15f857af2943a4aa282d04ff71f860352ad3291b](https://github.…
-
# Summary
|New Failures|gcc|g++|gfortran|Previous Hash|
|---|---|---|---|---|
|Resolved Failures|gcc|g++|gfortran|Previous Hash|
|---|---|---|---|---|
|linux: RVA23U64 profile lp64d medlow multilib …
-
# Summary
|New Failures|gcc|g++|gfortran|Previous Hash|
|---|---|---|---|---|
|linux: RVA23U64 profile lp64d medlow multilib |1164/150|0/0|0/0|[1dd175a0ccdd0ff4e7cb6668164a4fe99e47015d](https://githu…
-
-
-
Hello there, I met a strange issue when using LLVM/Clang to build c code with RISC-V Vector extension enabled, see test code here https://godbolt.org/z/GreE5bTWo
I am expecting when passing `-O2 -m…
-
## Precommit CI Run information
Logs can be found in the associated Github Actions run: https://github.com/ewlu/gcc-precommit-ci/actions/runs/12079016741
## Patch information
Applied patches: 1 -> 1
A…