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Last week, I implemented *probe* related stuff in Chisel binder (chipsalliance/chisel#3668). In CIRCT, `firrtl.ref.rwprobe` needs a `target` attribute with `InnerRefAttr` type. So I filled `inner_sym`…
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https://github.com/llvm/circt/actions/runs/6789634524/job/18457283622
https://github.com/llvm/circt/actions/runs/6800811293/job/18490222652
https://github.com/llvm/circt/actions/runs/6804514148/job/…
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### Describe the highlighting problem
Python staticmethod, classmethod, and property are builtin functions usable as decorators and they should have same highlighting.
### Example snippet that c…
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Seems it does not recognize tests inside tsx files:
I follow…
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### Describe the bug
When I use `:checkhealth nvim-treesitter`, I get the following error.
### To Reproduce
1. `:checkhealth nvim-treesitter`
### Expected behavior
_No response_
### Output …
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Great work, as I have seen from the tree-sitter issues related to astro and this repo ;)
- Have read the issues on [the treesitter readme](https://github.com/nvim-treesitter/nvim-treesitter#modules…
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Presently, in the `firtool` pipeline, clock information is thrown away when `!firrtl.clock` is lowered to `i1`. This is sub-optimal since past the lowering to HW, it is difficult to reason about the …
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The following FIRRTL program
```python
circuit top_mod :
module top_mod :
input clock: Clock
input arst: AsyncReset
output fsm_170_next: UInt
reg fsm_170_state: UInt, clock …
drom updated
11 months ago
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Given:
```python
FIRRTL version 3.2.0
circuit Test:
module Test:
input i: { f: UInt, b: UInt }
output o: { f: UInt, b: UInt }
connect o, i
```
Then as expected I get:
```verilo…
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This is a tracking issue for the first steps towards implementing a hardware description language for Tydi types.
Currently the Tydi crate provides modules with the logical and physical stream type…