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### What new feature should Elvish have?
I came across this while doing my usual RISC-V shenanigans: https://github.com/u-root/gobusybox
Sophgo uses u-root as part of their bootloader which is super…
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@kaashoek Hi, I think the bug reported by #5 is still a problem. I am trying to explain in detail.
This bug is related to instruction cache (ICache) in hardware.
1. Process `A` loads its code to …
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### Bug Description:
When executing the `amoxor.d a1, s4, (s4)` instruction, a discrepancy was observed between the behavior of Spike and NutShell processors. Specifically, when the value of register…
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The issue is opened to include all the changes in OMR for eclipse/openj9#5058 to enable RISCV 64 bit as follows:
https://github.com/eclipse/omr/pull/4431, https://github.com/eclipse/omr/pull/4432, ht…
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I have built a RISC-V multicore emulator. Is it possible to run this OS on my own emulator rather than QEMU? At this stage, it can run a binary file designed for multicore programs by checking mhartid…
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Hi, here is a problem I'm facing while enabling rust-vmm CI for RISC-V.
Feel free to leave your suggestions. Thanks in advance.
**Background:**
Buildkite doesn't support RISC-V agents platform.
…
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- Please review change : https://review.tizen.org/gerrit/#/c/platform/core/ml/nnfw/+/303102/
- For someone who cannot access the gerrit :
```diff
diff --git [a/compiler/pp/include/pp/Indente…
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The restrictions on LR/SC sequences that guarantee progress ("10.3. Eventual Success of Store-Conditional Instructions" in the unprivileged RISC-V spec) state that:
> • The loop comprises only an L…
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## Reproducing
Similar to that of issue #12209, but using latest master from Nuttx upstream.
QEMU is still 6.2 but OpenSBI firmware is v1.0, as the default v0.9 is no longer supported but latest S-…
yf13 updated
6 months ago
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Would it make sense to add an appendix to the RISC-V spec that lists all instructions alphabetically and describes them succinctly? This would be similar to the Appendix A of the "The RISC-V Reader" b…