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## Precommit CI Run information
Logs can be found in the associated Github Actions run: https://github.com/ewlu/gcc-precommit-ci/actions/runs/11804184723
## Patch information
Applied patches: 1 -> 1
A…
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Would it make sense to add an appendix to the RISC-V spec that lists all instructions alphabetically and describes them succinctly? This would be similar to the Appendix A of the "The RISC-V Reader" b…
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# RISC-V from scratch 1: Introduction, toolchain setup, and hello world!
A post that discusses what RISC-V is and why it's important, teaches readers how to install the GNU RISC-V toolchain, and walk…
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## Precommit CI Run information
Logs can be found in the associated Github Actions run: https://github.com/ewlu/gcc-precommit-ci/actions/runs/11855617930
## Patch information
Applied patches: 1 -> 2
A…
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Hi,
I’m looking to contribute to BOLT by enhancing the accuracy of edge weight estimation for the AArch64 and RISC-V platforms. This improvement would help us obtain more accurate edge weight infor…
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My colleagues and I are struggling to precisely define "hart" and are concerned the spec is misleading.
Section 1.1 paragraph 2 states "A RISC-V compatible core might support multiple RISC-V-compat…
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While working on #35, I realized that the `relocTargetBits` method of `IsRelocationType` is not capable of handling certain relocation types in PowerPC code. To recap:
https://github.com/GaloisInc/…
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When compiling a program which uses a global symbol and targets `riscv*`, it will generate a sequence instructions for calculating address:
```
foo:
lui a0, %hi(Var)
addi a0, a0, %lo(Var)
`…
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**Describe the bug**
RTT console support for `openocd` was added to `west` in 18f45b5f063 .
It wasn't immediately clear how to use it on any board. Luckily some folks on Discord provided some po…
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### Describe problem solved by the proposed feature
关联 https://github.com/RT-Thread/rt-thread/pull/9511#discussion_r1796327187
https://github.com/RT-Thread/rt-thread/blob/906d1caea6f82dcb45dc192…