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**Describe the bug**
RTT console support for `openocd` was added to `west` in 18f45b5f063 .
It wasn't immediately clear how to use it on any board. Luckily some folks on Discord provided some po…
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### Describe problem solved by the proposed feature
关联 https://github.com/RT-Thread/rt-thread/pull/9511#discussion_r1796327187
https://github.com/RT-Thread/rt-thread/blob/906d1caea6f82dcb45dc192…
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# p0: Running Rust code on bare-metal RISC-V (in QEMU) · Meyer Zinn
[http://localhost:1313/posts/2023/03/04/running-rust-code-on-bare-metal-risc-v-in-qemu/](http://localhost:1313/posts/2023/03/04/r…
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Hello,
MoreFuzz or metholds mentioned in the article can be ported to other ISAs not only RISC-V?
Looking forward to hearing from you, Thank you.
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Should be possible with some tweaks and extensions to the Toit build pipeline.
Initial testing is showing underlying compatibility with ESP-IDF; just a matter of identifying and abstracting all of …
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## 说明
问题背景:
涉及软件包: b3sum
涉及软件包地址: https://github.com/BLAKE3-team/BLAKE3
所需技能:
其它:
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please change
"Built on RISC-V and secured by Proof-of-Work, CKB is the most flexible and interoperable Layer 1 in the blockchain industry."
to
"Built on RISC-V and secured by Proof-of-Work…
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### Location
This affects our [platform support documentation](https://github.com/rust-lang/rust/blob/4c8bb79d9f565115637cc6da739f8389e79f3a29/src/doc/rustc/src/platform-support.md).
It specifically…
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Depends: #438
Solvers may wish to develop RISC-V solutions and/or translations locally. It isn't immediately obvious how to do so, since it differs from the native architecture of most consumer de…
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For UEFI_030, what does "Enable address translation" mean?
Technically, when S-mode is implemented, the RISC-V Privileged Architecture does not provide any way to disable address translation for pr…