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I think you should include AD and DA converters. Although these components are not standard internally in FPGAs, they are widely used in digital systems.
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### What is the expected enhancement?
The following circuit has depth 10:
```qasm
OPENQASM 2.0;
include "qelib1.inc";
qreg q[4];
cx q[0],q[1];
cx q[1],q[0];
cx q[2],q[1];
cx q[0],q[1];
cx …
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### What is your issue?
Hi everyone.
I am using quimb to optimize QAOA circuit. In the documentation, there is the example of " Bayesian Optimizing QAOA Circuit Energy" doing that for 3-reg grap…
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Currently PoLo Nodes (Powered LoRaNodes) are running bird call detection algorithm which provides LoRaWAN/MQTT packets which consists data from 8 bird calls rather than 1 per each packet. we need a m…
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This is on 18.11. We're seeing many errors such as:
```
[Fri Jan 18 12:15:13.189289 2019] [cgi:error] [pid 10510:tid 139835536762624] [client 81.152.140.227:58989] AH01215: [Fri Jan 18 12:15:13 2019…
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I'm not sure I understand what's happening, but I use `LayoutTransformation` and I recently hit a bug where `LayoutTransformation` isn't producing the desired output. It's actually non-deterministic, …
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In the files denmat.f90, mean.f90, dfconstrain.f90, electronflux.f90, there are notations
!! DO SUMMA (parconsplit.ne.0 and sparsesummaflag.eq.2, "circ")
!! AND DO HOPS
The subroutine…
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**Describe the bug**
Recently, in #1784, we added ISA checks inside bodies of control flow operations. @ashsaki found an example similar to the one below, where a valid circuit is labeled as invali…
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When redrawing the same circuit with a draw command, the labels disappear.
Code to reproduce:
```
import lcapy
cct = lcapy.Circuit("""
Vin 1 0_1 DC Vin; down
…
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**Describe the bug**
![image](https://user-images.githubusercontent.com/22888402/128174520-ef7b4907-d10d-46d8-b828-d9a2b3fb8157.png)
A clear and concise description of what the bug is.
**Ex…