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Consider:
```firrtl
FIRRTL version 3.0.0
circuit RWProbePortDedup: %[[
{
"class": "firrtl.transforms.MustDeduplicateAnnotation",
"modules": ["~RWProbePortDedup|A","~RWProbePortDedup|B"]
}…
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When deduplicating modules, inspect more than the root inner symbol and perform the same renaming/updating logic for each inner symbol found (not just for fieldID == 0).
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The following FIRRTL program
```python
circuit top_mod :
module mod0 :
input inp: UInt
output out: UInt
out
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Code path not under test, should probably be an error (?).
Input:
```
firrtl.circuit "Mem2" {
firrtl.module @Mem2(in %clock: !firrtl.clock, in %rAddr: !firrtl.uint, in %rEn: !firrtl.uint, out …
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Currently, CIRCT will squash "raw" FIRRTL external module parameters into string parameters. This produces a difference with the SFC. Consider:
```
circuit Foo:
extmodule Bar:
output a: UI…
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Consider the following circuit:
```scala
circuit Bar:
module Bar:
input a: UInt[1]
output a_0: UInt
a_0 ()
}) {annotations = [], portAnnotations = [[], []], portDirections = …
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As found by @Ramlakshmi3733, large designs seem to exhibit bad scaling performance with the existing FIRRTL Parser's annotation parsing/scattering. I don't have a minimal example, but a "large" desig…
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The following FIRRTL program
```python
circuit top_mod:
module top_mod:
input a: { b: UInt }
input a_b: UInt
```
Compiled with `firtool` produces this Verilog:
```verilog
modu…
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```
********************
Slowest Tests:
--------------------------------------------------------------------------
3.78s: CIRCT :: Dialect/FIRRTL/inliner-nyi.mlir
3.77s: CIRCT :: Dialect/FIRRTL/i…
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This is the Grand Central (GCT) Taps variant of #3494. GCT Taps does not work on a deduplicated design. We need to fix this with a better representation for XMRs that works with dedup. Dedup and annot…