-
A subset of style lint rule findings point to issues that are trivially fixable and should be made easy to apply, e.g. in the form of patches.
e.g.
* add/fix end labels
* delete extraneous semico…
-
Task:
Align struct union members.
qualifier, type [dim] | id | [= default]
-----|-----|----
`rand int` | `x;` | ` `
`int` | `xxxx;` | ` `
`int` | `xx` | `= 0;`
`int` | `x` | `= 1,`
` ` |…
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## Result from CocInfo
```
## versions
vim version: VIM - Vi IMproved 8.2 8022815
node version: v16.6.1
coc.nvim version: 0.0.80-8f2b91b437
coc.nvim directory: /home/khanhnguyen/.vim/p…
-
When attempting to run tests on MacOS, the following pops up:
https://github.com/google/verible/pull/735/checks?check_run_id=2255601244#step:4:188
Not sure if this is a version issue of Python (…
-
Hi,
I want to work on signal dependencies based on the CST JSON output of SystemVerilog modules.
It would be really helpful if I can get the defined port names, signal, wire, reg names in JSON outpu…
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Go through https://reports.opentitan.org/hw/ip/rv_core_ibex/lint/ascentlint/latest/results.html and try to understand/fix all lint errors. Talk to @msfschaffner to waive the ones we don't care about (…
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Input:
```systemverilog
module m;
if (x) begin:z1
assign x=y;
end
else
if (y) begin:z2
assign z=y;
end
endmodule
```
Currently formats to:
```systemverilog
module m;
if (x) begi…
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- [ ] Evaluate if we can move to c++17, by checking all the (sometimes pretty old) distributions we support when building. **No** : all compilers can do c++17, but not all of them provide the `` head…
-
Resolution in #625 was to clamp 0.0.49 to some older version of Kythe. Did a quick test today to see if the latest version `0.0.52` would work, but different issues emerge:
Using this in WORKSPACE
…
-
**Test case**
```systemverilog
module m;
export "DPI-C" function mhpmcounter_get;
endmodule
```
**Actual output**
```systemverilog
module m;
export "DPI-C"
function mhpmcounter_g…