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In init_regs function, cpsr is assigned with EL1.
``` c
367 thread->regs.pc = (uint64_t)thread_std_smc_entry;
xxx
373 thread->regs.cpsr = SPSR_64(SPSR_64_MODE_EL1, SPSR_64_MODE_SP_E…
MrVan updated
7 years ago
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Error after trying to build a pine64 SD images in the following options.
`$ sudo ./compile.sh BUILD_DESKTOP=no KERNEL_ONLY=no BOARD=pine64 BRANCH=default RELEASE=xenial PROGRESS_LOG_TO_FILE=yes PROGR…
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The build for the ZynqMP platform fails on the integration branch, with the following error:
```
plat/arm/common/aarch64/arm_common.c: In function 'plat_get_syscnt_freq':
plat/arm/common/aarch64/arm_…
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Has there been any thought put into providing a driver for storing and retrieving nv parameters from flash devices? Here is the current use case:
- BL2 DDR init code needs to retrieve tuning paramete…
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Hi,
We use only BL31 from ATF, BL1 and BL2 are replaced by our custom boot loaders and S-EL1 is not supported. We wanted to handle all secure requests coming to EL3 in BL31 itself.
Is there any plan…
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A release build for the mt8173 platform with a LOG_LEVEL greater than or equal to 40 fails with the following error:
```
In file included from plat/mediatek/mt8173/drivers/spm/spm.c:31:0:
plat/mediat…
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Hi ATF Team,
mmu setup is called at each BL stages (BL1, BL2, BL31 ...).
In current ATF, correct me if I am wrong but there is no way to bypass xtable_create and call the mmu enable macro with the TT…
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clean_dcache_range is executed from bl31_entrypoint before calling el3_exit. But, the EL3 runtime stack (SP_EL0 ) which will be used for handling the next SMC call is updated in psci_ns_context from f…
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The SCR_EL3.SIF (Secure Instruction Fetch) bit should be enabled in BL1 and BL31 common architectural setup code. When in secure state, this disables instruction fetches from
Non-secure memory.
We pr…
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I am having a problem with Thermos Build 32. Crash log: [http://pastebin.com/raw/FKk1bncx](http://pastebin.com/raw/FKk1bncx).
I have tested this with Vanilla. It worked perfectly fine.