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If a circuit has an uninformed reset, this is currently printing the whole module body. This should just print the module definition (or the port once source locators are hooked up to those). This sho…
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[AndOfPadS](https://github.com/llvm/circt/blob/08b407136823ad8516e16674abdb297688cf5206/include/circt/Dialect/FIRRTL/FIRRTLCanonicalization.td#L311-L315) will always keep the most significant bit of t…
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Consider the following FIRRTL text. This is a sketch of what a designer would write using `when`/`elsewhen`/else` Chisel constructs. (This is derived from a classic Chisel example, https://github.com/…
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For different cocktails of optimizations, Verilog generated from FIRRTL Dialect can produce different randomizations for the same seed.
Consider the following circuit with three registers:
```sc…
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As of 1.1.0, version preamble is required for FIRRTL files. Include an appropriate version string when emitting FIRRTL so it may be parsed by tools expecting it.
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The Scala FIRRTL Compiler (SFC) uses a special annotation, [`firrtl.stage.RunFirrtlTransformAnnotation`](https://www.chisel-lang.org/api/firrtl/latest/firrtl/stage/RunFirrtlTransformAnnotation.html) t…
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Probably we can make DropConstPass CircuitOp and parallelize the type conversion as we are doing in VBToBVPass
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Currently, FIRRTL passes that rely on the existence of specific annotations have to be explicitly created by a `firtool` user. Instead, we could create all passes that are necessary based on the annot…
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IMDCE contains a simple constant prop, which appears to not be working with the addition of `const` types. cc @trilorez @uenoku.
`./bin/circt-opt -pass-pipeline='builtin.module(firrtl-imdeadcodee…
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### Describe the bug
This piece of code, which is completely fine to python, produces an error on treesitter:
```python
class Foo:
foo: Annotated[
list[AnotherType],
some_f…