-
```
suspected report that 64 bit windows code fails to build if ssse3 is not
enabled.
```
Original issue reported on code.google.com by `fbarch...@google.com` on 19 Aug 2014 at 1:02
-
```
suspected report that 64 bit windows code fails to build if ssse3 is not
enabled.
```
Original issue reported on code.google.com by `fbarch...@google.com` on 19 Aug 2014 at 1:02
-
This is a GSoC task.
Some is already done: There are SIMD_PARA_SHA256 and SIMD_PARA_SHA512 defined in some header files. And some formats does use them in index calculations (although they are curren…
-
It seems that the nehalem build is broken, we should fix this. Example failure
```
Instruction: vpmaxsd -0x7(%r11d,%ebx,4), %ymm15, %ymm7
Maybe read set: { %ebx %r11d %ymm15 }
Must write set: { …
-
```
suspected report that 64 bit windows code fails to build if ssse3 is not
enabled.
```
Original issue reported on code.google.com by `fbarch...@google.com` on 19 Aug 2014 at 1:02
-
```
suspected report that 64 bit windows code fails to build if ssse3 is not
enabled.
```
Original issue reported on code.google.com by `fbarch...@google.com` on 19 Aug 2014 at 1:02
-
```
suspected report that 64 bit windows code fails to build if ssse3 is not
enabled.
```
Original issue reported on code.google.com by `fbarch...@google.com` on 19 Aug 2014 at 1:02
-
```
suspected report that 64 bit windows code fails to build if ssse3 is not
enabled.
```
Original issue reported on code.google.com by `fbarch...@google.com` on 19 Aug 2014 at 1:02
-
When dealing with SIMD instructions stes, we need to know if a CPU is an actual AMD to acces SSE4A intrinsics. Currently AMD detection is clumped with X86.
-
```
suspected report that 64 bit windows code fails to build if ssse3 is not
enabled.
```
Original issue reported on code.google.com by `fbarch...@google.com` on 19 Aug 2014 at 1:02