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Hello, I am attempting to write a testbench in verilog for the Arty A7 in order to send a simple message from the board to a mobile device, but am having trouble translating how the ethernet frame var…
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Hi,
I'm having troubles compiling the tf2_erfnet_cityscapes_512_1024_54G_1.4 model from the AI Model Zoo for DPUCADF8H for Alveo U250. I downloaded the quantized model from the Github.
The comma…
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Hello, I'm a researcher wishing to achieve p2p data transfer from FPGA (Xilinx Alveo U50) to an AMDGPU. I read the https://rocm.docs.amd.com/en/latest/how-to/gpu-enabled-mpi.html and find that ucx is …
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Hi @alexforencich ,
First of all, thank you for sharing this wonderful library.
I want to implement this project on Alveo U200 card. I follow verilog-ethernet/example/AU200/fpga_10g/README.md,
run…
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Hi
I am trying to bring up a Alveo U50 with corundum. Managed to get it running with a DAC but when I try to switch to optical transciever I can't get it to create a link . I have read in the documen…
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Hi all,
Whishing you have a good day.
Our project is to **analyzing the incoming package data from Telecom network, filter the packages, modify the packages, grouping some packages, sending to h…
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Once #210 has been resolved we then need to build a way of annotating streamed media online. This will allow us to enrich the metadata but will need to be mediated if the user is unknown to us.
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Hi everyone,
I met the problem as the title shown when I try to connect FPGA to host PC.
The environment is:
FPGA: Alveo U200
Vivado 2020.2
Ubuntu 20.02
error report:
sudo ./load_driver.sh …
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I'm working on a project that will be intercepting and modifying TCP traffic as it crosses between the two ports on the Alveo U50DD. Now the functionality is working, I am looking to measure and optim…
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Hi
I am a starter for Alveo and SDAccel.
I met an issue when I used the getting-started-rtl-kernels example,
https://github.com/Xilinx/SDAccel-Tutorials/tree/master/docs/getting-started-rtl-k…