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Currently I'm trying to understand the way to add a DMA device into chipyard design. Based on the suggestion in https://github.com/ucb-bar/chipyard/issues/9, I have started with the example of BlockDe…
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Forgive me, I'm new to Chisel, so this could be user error.
I am struggling to get testing to work. I get tons of warnings that look like this:
```
WARNING: external module "AsyncResetReg"(tl.c…
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@7FM noted:
> I find the logging sometimes a bit too verbose, especially when the `containingOp` is very large. A hacky workaround that I sometimes use OoT is something like `mlir::emitError(OpBuilde…
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**Type of issue**: Bug Report
**Please provide the steps to reproduce the problem:**
I get the Error `java.lang.OutOfMemoryError: Required array length 2147483640 + 18 is too large` when I t…
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Paths to memory ports are always marked as `OMDeleted`, when I would expect them to point to a port on the lowered module.
There is the same problem with the old version of OMIR, and any annotations …
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This project aims to apply information found using the firrtl interpreter's run-time instrumentation of values passing through a node.
- Run a firrtl circuit with instrumentation turned on
- This …
chick updated
6 years ago
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This is not a bug report per se, but more of a question.
See listing 15 from the specs:
![{real: {word:UInt, valid:UInt, flip ready:UInt}
imag: {word:UInt, valid:UInt, flip ready:UInt}}](https:/…
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If a circuit contains a bind-under-bind, then this can't be lowered to SystemVerilog without transformation. It would be simpler (for now) to make any nested bind a verifier error.
E.g., the follow…
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bug report
**What is the current behavior?**
```
$ cat input1.firrtl
circuit main :
module main :
node a = dshl(UInt(0), rem(UInt(1), SInt(0)))
```
```
$ java -cp firrtl.jar firr…
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### Checklist
- [x] Did you specify the current behavior?
- [x] Did you specify the expected behavior?
- [x] Did you provide a code example showing the problem?
- [x] Did you describe your envir…