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```elixir
defmodule Ibex.Tws.RequestOptions do
@moduledoc """
Constructs options maps for various TWS API requests, ensuring they adhere to expected formats and values.
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Is there anyway to set the reset vector to `0x80000000` through a parameter or config?
_Originally posted by @kevinhe5 in https://github.com/lowRISC/ibex/issues/2026#issuecomment-1548751210_
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## Observed Behavior
I simulated the simple system example using VCS, following the guide in https://github.com/lowRISC/ibex/blob/master/examples/simple_system/README.md
I build the simulati…
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Hello, I'm trying to run synthesis with Vivado, and it shows some error messages like these:
```
[Synth 8-1766] cannot open include file prim_assert_dummy_macros.svh ["../ibex_rtl/prim_assert.…
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### Test point name
[chip_sw_rv_core_ibex_alerts](https://github.com/lowRISC/opentitan/blob/316831f8c2199f2288dd57ac4aeaec3334b5dfb8/hw/top_earlgrey/data/chip_testplan.hjson#L3271)
### Host side…
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STR:
```
$ wget https://raw.githubusercontent.com/lowRISC/ibex/master/rtl/ibex_counters.sv
$ verilog_format ibex_counters.sv
rtl/ibex_counters.sv:65:1: syntax error, rejected "`else" (https://g…
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As someone who supports IBEX I want the EPICS archiver system in use to be easy to use and update, as such I would like to use the Archiver Appliance rather than the system currently incorporated into…
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In the "groups"-tab in the edit configuration window: blocks not assigned to a group are available to be added to any group, therefore these should always be visible in the "available" list, even when…
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It would be very nice to have GDB debug support over JTAG using the existing work in DM/DMI/OpenOCD. A good example where the RISC-V debug module was added to the Ibex RV32IMC can be found in these la…
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While building simulation from Ibex Repo folder, I got this error.
_sh-5.0$ fusesoc --cores-root=. run --target=sim --tool=verilator --setup --build lowrisc:ibex:demo_system
ERROR: 'lowrisc:ibex:d…