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Reported by: **[daschuer](https://github.com/daschuer)**
Date: 2014-12-28T17:07:07Z
Status: Confirmed
Importance: Wishlist
Launchpad Issue: [lp1406117](https://bugs.launchpad.net/bugs/1406117)
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I…
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Listed below are CpuMath enhancement suggestions raised during PR reviews for SSE and AVX intrinsics but only documented for future follow-up.
The individual issue pages that expand each issue are …
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Since RyuJIT already supports this, I think we just need these things:
- [x] Type layout work for Vector64/Vector128/Vector256. This is basically a port of dotnet/coreclr#15961. It might look simil…
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Rather than interoping to zlib when the Crc32 intrinsics are available on Arm and x86/x64
https://github.com/dotnet/runtime/blob/995224db011f77eb095279122244704ccca01d5f/src/libraries/System.IO.Com…
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On Windows, Visual studio 2022, no AVX, AMD Ryzen 9 5950x.
```
wuffs 0.3, decoding to WUFFS_BASE__PIXEL_FORMAT__RGB
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doDecodeFromBufferWithWu…
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Currently, ISPC only has native support for a handful of transcendental functions and only at single precision. Recently, Intel has open sourced their SVML library (see https://github.com/numpy/SVML)…
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Create a 2D rasterizer, rich drawing primitives, and 2D graphics library
suitable for resource constrained embedded systems (e.g. ARM Cortex-M)
to be used in industrial controls, home appliances, me…
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I tried to compile some code with latest headers (from HEAD) using x86_64-w64-mingw32-g++ 7.4.0 crosscompiler shipped with Cygwin. I got following errors:
```
In file included from /usr/x86_64-w64…
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Intel SHA instructions assist with hardware acceleration of the SHA-1 and SHA-256 hash algorithms.
Current Ryzen processors that support these instructions can reach SHA-256 speeds of around 2 GB/s…
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We should add WASM simd128 implementations of as many SSE/SSE2/etc. functions as possible.
If a function has a WASM implementation, please check it off the list.
Not all functions will have reas…