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```
target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v16:16:16-v24:32:32-v32:32:32-v48:64:64-v64:64:64-v96:128:128-v12
8:128:128-v192:256:256-v256:25…
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On RDNA gpus, shift vector instructions are much faster when the shift amount is a splat constant. However, we seem to emit non-splat shifts for int4 matvec from LLama2:
Input
```mlir
func.func @…
kuhar updated
3 months ago
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There is a plan to enable AOT Inductor for Intel GPU in PyTorch 2.6. While working on the design, PyTorch Team realized that the Triton kernel is now saved as SPIR-V(IR), while CUDA is cubin(device c…
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I get a crash when compiling shaders to SPIR-V with printf. It seems to be a bit inconsistent and from what I can tell there are unit tests of this that seem to pass, so I think it might be some memor…
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This issue is from Discord conversation https://discordapp.com/channels/750717012564770887/750717499737243679/943879544006381638
### Expected Behaviour
I want to compile [my shader](https://gi…
hatoo updated
2 weeks ago
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## Motivation
Currently, SPIR-V backend has no way distinguish decorated types (in SPIR-V, decoration instructions modifies types/variables/functions/etc attributes). for example, in the below code…
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I have a function that loads spv file:
```cpp
std::vector loadSpv(std::string path) {
std::ifstream file(path, std::ios::ate | std::ios::binary);
if (!file.is_open()) {
throw …
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This is a tracking bug for implementing lowering towards the SPIR-V dialect. It will be periodically updated to provide the current status. Anybody interested in helping is very welcome to pick up tas…
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**Description**
I cannot define static const member field for a struct if they need to be computed from a template parameter struct's static const member field. This godbolt shows what I mean: https:/…
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When a 64-bit immediate value is used in a switch construct, the SPIR-V emitter splits the 64bit int into 2 32-bit integers, causing a bad instruction to be generated:
```
OpSwitch %5 %8 429496729…