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Add a config setting to specify the verible-verilog-format flags.
E.g.:
``` yaml
verible_flags: --net_variable_alignment=align
```
(BTW: thanks for creating this, just what I was looking for :)…
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Thank you for this awesome project. I was wondering if the following either or both of the following features can be supported:
- `define tokens can be added to the syntax tree. I would like to us…
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**Summary**
Based on an ongoing porting of OpenTitan across simulators, we are finding some interesting issues on compatibility. Wondering if we can extract a rule-set/policy and make it part of Ve…
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**Summary**
The google and [lowRISC style guides](https://github.com/lowRISC/style-guides/blob/master/VerilogCodingStyle.md#generate-constructs) discourage the use of `generate` regions and separat…
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```
+ bazel test -c opt --show_progress_rate_limit=10.0 //...
Extracting Bazel installation...
Starting local Bazel server and connecting to it...
Loading:
Loading: 0 packages loaded
DEBUG: Rul…
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See https://github.com/google/verible/runs/1520501401 for example
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**Summary**
Recently found this on OpenTitan, see:
https://github.com/lowRISC/opentitan/issues/4355#issuecomment-736782490
Wondering if this will be caught in Verible using existing rules.
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We'd like to understand how you use the various documentation sources. If you could please fill in this survey it would be appreciated:
[Verilator Documentation Survey (Google Form)](https://forms.…
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Since kythe was added as a dependency, most travis-builds have been timing out.
First bad:
https://travis-ci.org/github/google/verible/jobs/739104819
Last good:
https://travis-ci.org/github/go…