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Synopsys VCS-MX supports not only (System)Verilog as is the case with the backend right now but also VHDL, allowing mixed-language simulation.
Some pointers:
- http://www.vlsiip.com/vcs/
- http://s…
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There is Xilinx IP that checks for violations of the AXI protocol on a bus: https://www.xilinx.com/products/intellectual-property/axi_protocol_checker.html
When designing a HDL core through SNAP it…
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Currently the CI rely on a current job that "count" the number of completed siblings jobs in order to trigger the publication step to the main litex-hub package: https://github.com/hdl/conda-eda/blob/…
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In a FPGA design ff and bram values can be initialized via the bitstream. This saves routing resources since it doesn't require a reset signal to be routed within each clock domain. [0]
Example ver…
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Hello.
DigitalJS has a really cool feature to improve schematic readability by generating arithmetic operations fused with constants: [code source](https://github.com/tilk/digitaljs/blob/a541f0ff32…
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SystemVerilog is a very popular hardware description language (HDL). Google is working on improving the ecosystem around this language, including developing linting and code fixing tooling. It would b…
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Add support for bringing VHDL types into Python.
The obvious ones are enumeration and physical types.
**Enumeration type**
```vhdl
type MULTI_LEVEL_LOGIC is (LOW, HIGH, RISING, FALLING, AMBIGU…
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```
Add HTTP header "X-OpenHandle" (or "X-Open-Handle" ?) with value of what?
This would make it easy to verify that the service is an OpenHandle service.
What should be the value though? One could …
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Requesting for a RIPE handle which is gone from the RIPE database gives a 502 bad gateway
Example: https://cp-aec-stg.cert.at/api/1.0/ripe/settings/5086/ORG-MAA1-RIPE
ghost updated
4 years ago
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Hi, My name is Welly. Currently I want to implement your code on my system with Velodyne Lidar VLP-16. Would you like to help me to set up the environment on Linux? I have installed and download the r…